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? semiconductor components industries, llc, 2006 november, 2006 ? rev. 0 1 publication order number: NCP1562A/d NCP1562A, ncp1562b high performance active clamp/reset pwm controller the ncp1562x is a family of voltage mode controllers designed for dc ? dc converters requiring high ? efficiency and low parts count. these controllers incorporate two in phase outputs with an overlap delay to prevent simultaneous conduction and facilitates soft switching. the main output is designed for driving a forward converter primary mosfet. the secondary output is designed for driving an active clamp circuit mosfet, a synchronous rectifier on the secondary side, or an asymmetric half bridge circuit. the ncp1562 family reduces component count and system size by incorporating high accuracy on critical specifications such as maximum duty cycle limit, undervoltage detector and overcurrent threshold. two distinctive features of the ncp1562 are soft ? stop and a cycle skip current limit with a time threshold. soft ? stop circuitry powers down the converter in a controlled manner if a severe fault is detected. the cycle skip detector enables a soft ? stop sequence if a continuous overcurrent condition is present. additional features found in the ncp1562 include line feed ? forward, frequency synchronization up to 1.0 mhz, cycle ? by ? cycle current limit with leading edge blanking (leb), independent under and overvoltage detectors, adjustable output overlap delay, programmable maximum duty cycle, internal startup circuit and soft ? start. features ? dual control outputs with adjustable overlap delay ? >2.0 a output drive capability ? soft ? stop powers down converter in a controlled manner ? cycle ? by ? cycle current limit ? cycle skip initiated if continuous current limit condition exists ? voltage mode operation with input voltage feedforward ? fixed frequency operation up to 1.0 mhz ? bidirectional frequency synchronization ? independent line undervoltage and overvoltage detectors ? accurate programmable maximum duty cycle limit ? programmable maximum volt ? second product ? programmable soft ? start ? internal 100 v startup circuit ? precision 5.0 v reference ? these are pb ? free devices* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. tssop ? 16 dt suffix case 948f x = current limit (a, b) a = assembly location wl, l = wafer lot y = year ww, w = work week marking diagrams ncp 562x alyw typical applications ? telecommunications power converters ? low output voltage converters using control driven synchronous rectifier ? industrial power converters ? 42 v automotive system ? atx power supplies http://onsemi.com 1 16 so ? 16 d suffix case 751b see detailed ordering and shipping information in the package dimensions section on page 24 of this data sheet. ordering information ncp1562xg awlyww
NCP1562A, ncp1562b http://onsemi.com 2 figure 1. detailed block diagram v in 1 16 v aux i inhibit i start disable + ? v aux(on) + ? central logic disable_vref 5.0 v reference v aux p.o.r. bias v ref 8 s dominant reset latch r q c aux v aux(on) / v aux(off1) / v aux(off2) + ? + ? one shot pulse v uv soft ? stop complete thermal shutdown stop uvov detector uvov v in r2 r1 2 v 3 v v ref c t r t 6 rtct 500 a sync dmax clock oscillator 7 sync + ? cskip comparator + ? v cskip cskip control logic v ref i cskip(c) i cskip(d) 12 cskip c cskip clock + ? not saturated + ? 3.6 v saturation comparator s dominant reset latch r q q clock ff reset delay logic enable_output out1 15 v aux 14 pgnd out2 13 v aux 11 270 k 20 k v ref ? + pwm comparator ? + soft ? start comparator ? + ff comparator + ? 0.2 v 3 v + ? v in r ff c ff v ea ff 3 5 gnd ff reset ilimit comparator + ? + ? 0.2 v = a ver. (0.5 v = b ver.) out fixed 80 ns leb clock enable not saturated soft ? start soft ? stop control logic stop v x soft ? start complete soft ? stop complete v ref i ss(c) i ss(d) 10 ss c ss 4 cs enable_output 1 v 2 t d r d 9 v x
NCP1562A, ncp1562b http://onsemi.com 3 pin function description pin symbol description 1 v in connect the input line voltage directly to this pin to enable the internal startup regulator. a constant current source supplies current from this pin to the capacitor connected to the v aux pin, eliminating the need for a startup resistor. the charge current is typically 10 ma. maximum input voltage is 100 v. 2 uvov input supply voltage is scaled down and sampled by means of a resistor divider. the same pin is used for both undervoltage (uv) and overvoltage (ov) detection using a novel architecture (patent pending). the minimum and maximum input supply voltage thresholds are adjusted independently. a uv condition exists if the uvov voltage is below 2.0 v and an ov condition exists if the uvov voltage exceeds 3.0 v. the undervoltage threshold is trimmed during manufacturing to obtain 3% accuracy allowing a tighter power stage design. both the uv and ov detectors have a 100 mv hysteresis. 3 ff an external r ? c divider from the input line generates the feedforward ramp. this ramp is used by the pwm comparator to set the duty cycle, thus providing direct line regulation. an internal pulldown transistor discharges the external capacitor every cycle. once discharged, the capacitor is ef fectively grounded until the next cycle begins. 4 cs overcurrent sense input. if the cs voltage exceeds 0.2 v (or 0.5 v in the ncp1562b) the converter operates in cycle ? by ? cycle current limit. once a current limit pulse is detected, the cycle skip timer is enabled. internal leading edge blanking pulse prevents nuisance triggering during normal operation. the leading edge blanking is disabled during soft ? start and output overload conditions to improve the response to faults. 5 gnd control circuit ground. all control and timing components that connect to gnd should have the shortest loop possible to this pin to improve noise immunity. 6 r t c t an external r t ? c t divider from v ref sets the operating frequency and maximum duty cycle of out1. the maximum operating frequency is 1.0 mhz. a sawtooth ramp between 2.0 v and 3.0 v is generated by sequentially charging and discharging c t . the peak and valley of the ramp are accurately controlled to provide precise control of the duty cycle and frequency. the outputs are disabled during the c t discharge time. 7 sync proprietary bidirectional frequency synchronization architecture allows two ncp1562 devices to synchronize together. the lower frequency device becomes the slave. it can also synchronize to an external signal. 8 v ref precision 5.0 v reference. maximum output current is 5.0 ma. it is required to bypass the reference with a capacitor. the recommended capacitance range is between 0.047 f and 1.0 f. 9 v ea the error signal from an external error amplifier is fed to this input and compared to the feedforward ramp. a series diode and resistor offset the voltage on this pin before it is applied to the pwm comparator inverting input. an internal pullup resistor allows direct connection to an optocoupler. 10 ss a 10 a current source charges the external capacitor connected to this pin. duty cycle is limited during startup by comparing the voltage on this pin to the feedforward ramp. under steady state conditions, the ss voltage is approximately 3.8 v. once a uv, ov, overtemperature or cycle skip fault is detected, the ss capacitor is discharged in a controlled manner with a 100 a current source. the duty cycle is then slowly reduced until reaching 0%. 11 t d an external resistor between this pin and gnd sets the overlap time delay between out1 and out2 transitions. 12 cskip the converter is disabled if a continuous overcurrent condition exists. the time to determine the fault and the time the converter is disabled are programmed by the capacitor (c cskip ) connected to this pin. the cycle skip timer is enabled after a current limit fault is detected. once enabled, c cskip is charged with a 100 a source. if the overcurrent fault is removed before entering the soft ? stop mode, the capacitor is discharged with a 10 a source. once c cskip reaches 3.0 v, the converter enters a soft ? stop mode and c cskip is discharged with a 10 a source. the converter is re ? enabled once c cskip reaches 0.5 v. if the condition resulting in overcurrent is cleared during this phase, c cskip discharges to 0 v. otherwise, it starts charging from 0.5 v, setting up a hiccup mode operation. 13 out2 secondary output of the pwm controller. it can be used to drive an active clamp/reset switch, a synchronous rectifier topology, or both. out2 has an adjustable leading and trailing edge overlap delay against out1. out2 has source and sink resistances of 12 (typ.). out2 is designed to handle up to 1.0 a. 14 pgnd ground connection for out1 and out2. tie to the power stage return with a short loop.
NCP1562A, ncp1562b http://onsemi.com 4 pin function description (continued) pin symbol description 15 out1 main output of the pwm controller. out1 has a source resistance of 4.0 (typ.) and a sink resistance of 2.5 (typ.). out1 is designed to handle up to 2.5 a. out1 trails out2 during a low to high transition and leads out2 during a high to low transition. 16 v aux positive input supply. this pin connects to an external capacitor for energy storage. an internal current source supplies current from v in to this pin. once the voltage on v aux reaches approximately 10.3 v, the current source turns off and the outputs are enabled. it turns on again once v aux falls to 8.0 v. if the bias current consumption exceeds the startup current, v aux will continue to discharge. once v aux reaches 7.0 v, the outputs are disabled allowing v aux to charge. during normal operation, power is supplied to the ic via this pin by means of an auxiliary winding. the startup circuit is disabled once the voltage on the v aux pin exceeds 10.3 v. if the v aux voltage drops below 1.2 v (typ), the startup current is reduced to 200 a.
NCP1562A, ncp1562b http://onsemi.com 5 maximum ratings (notes 1 and 2) rating symbol value unit line v oltage v in 100 v auxiliary supply, out1, out2 v aux , v outx 20 v all other inputs/outputs voltage v io 10 v all other inputs/outputs current i io 5.0 ma 5.0 v reference output current i ref 10 ma 5.0 v reference output v oltage v ref ? 0.3 to 6.0 v out1 peak output current (d = 2%) i out1 2.5 a out2 peak output current (d = 2%) i out2 1.0 a operating junction temperature t j ?40 to +125 c storage temperature range t stg ?55 to +150 c power dissipation (t a = 25 c, 2.0 oz cu, 1.0 sq inch printed circuit copper clad) dt suffix, plastic package case 948f (tssop ? 16) d suffix, plastic package case 751b (so ? 16) p d 0.75 0.95 w thermal resistance, junction to ambient (2.0 oz cu printed circuit copper clad) dt suffix, plastic package case 948f (tssop ? 16) 0.36 sq in 1.0 sq in d suffix, plastic package case 751b (so ? 16) 0.36 sq in 1.0 sq in r ja 155 133 120 105 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: pins 2 ? 16: human body model 2000 v per mil?std?883, method 3015. machine model method 160 v. pin 1 is the hv startup of the device and is rated to the max rating of the part, or 100 v. 2. this device contains latchup protection and exceeds 100 ma per jedec standard jesd78.
NCP1562A, ncp1562b http://onsemi.com 6 electrical characteristics (v in = 48 v, v aux = 12 v, v uvov = 2.3 v, v ea = open, v cskip = 0 v, v cs = 0 v, v ss = open, r t = 13.3 k , c aux = 10 f, c t = 470 pf, c out1 = c out2 = 100 pf, c uvov = 0.01 f, c cskip = 6800 pf, r d = 25 k , r sync = 5.0 k , c ref = 0.1 f, r ff = 29.4 k , c ff = 470 pf. for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted.) characteristic symbol min typ max unit startup control and v aux regulator v aux regulation (v uvov = 0 v) inhibit threshold v oltage startup threshold/v aux regulation peak (v aux increasing) operating v aux valley voltage minimum operating v aux valley voltage after turn ? on (v uvov = 2.3 v, v ea = 0 v) v inhibit v aux(on) v aux(off1) v aux(off2) ? 9.65 7.42 6.50 1.15 10.3 8.0 7.0 1.5 10.97 8.48 7.42 v minimum startup voltage (pin 1) i aux = 1.0 ma, v aux = v aux(on) ? 0.2 v v start(min) ? ? 23.2 v inhibit bias current v aux = 0 v i inhibit 70 170 270 a startup circuit output current v aux = v inhibit + 0.2 v v aux = v aux(on) ? 0.2 v i start1 i start2 7.16 4.03 9.3 6.1 11.3 8.1 ma startup circuit off ? state leakage current (v in = 200 v, v uvov = 0 v) t j = 25 c t j = ?40 c to 125 c i start(off) ? ? 25 ? 50 100 a startup circuit breakdown voltage (note 3) i start(off) = 50 a, t j = 125 c v br(ds) 100 ? ? v auxiliary supply current after v aux turn ? on outputs disabled v uvov = 0 v v ea = 0 v outputs enabled v ea = 4.0 v i aux1 i aux2 i aux3 ? ? ? 3.0 4.2 5.5 3.6 4.94 7.0 ma line under/overvoltage detector undervoltage threshold (v in increasing) v uv 1.979 2.05 2.116 v undervoltage hysteresis v uv(h) 0.074 0.093 0.118 v undervoltage ratio (v uv(h) /v uv ) v uv(ratio) 3.65 4.50 5.62 % overvoltage threshold (v in increasing) v ov 2.80 2.95 3.10 v overvoltage hysteresis v ov(h) 0.075 0.093 0.127 v offset current (v uvov = 2.8 v) i offset(uvov) 38 48 58 a offset current turn on threshold ( 5%, i offset(uvov) = 40 a) v offset(uvov) 2.4 2.6 2.8 v line feedforward peak voltage (volt ? second clamp) v ff(peak) 2.8 3.0 3.2 v discharge current (v ff = 0.5 v, v ss = 0 v) i ff(d) 8.5 ? ? ma offset voltage (v ff = 0 v, ramp down v ss ) v offset(ff) 0.118 0.185 0.268 v feedforward offset minus soft ? stop reset voltage (ff ? ss) 7 70 183 mv 3. guaranteed by design only.
NCP1562A, ncp1562b http://onsemi.com 7 electrical characteristics (continued) (v in = 48 v, v aux = 12 v, v uvov = 2.3 v, v ea = open, v cskip = 0 v, v cs = 0 v, v ss = open, r t = 13.3 k , c aux = 10 f, c t = 470 pf, c out1 = c out2 = 100 pf, c uvov = 0.01 f, c cskip = 6800 pf, r d = 25 k , r sync = 5.0 k , c ref = 0.1 f, r ff = 29.4 k , c ff = 470 pf. for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted.) characteristic symbol min typ max unit current limit and thermal shutdown cycle?by?cycle threshold v oltage (v out = 10 v) NCP1562A ncp1562b v ilim 191 476 203 495 217 512 mv propagation delay to output (v cs = v ilim to 1.0 v, leb disabled, v out = 10 v) t j = 25 c t j = ?40 c to 125 c t ilim ? ? 78 ? 90 110 ns thermal shutdown threshold (junction temperature increasing, note 4) t shdn ? 160 ? c thermal shutdown hysteresis (temperature decreasing, note 4) t h ? 25 ? c leading edge blanking offset voltage v leb(offset) ? 10 ? mv blanking time t leb 50 80 110 ns v ea threshold the disables leb (measured together with t leb ) v leb(dis) 4.1 ? ? v cycle skip current limit mode charge current (v cskip = 1.25 v) i cskip(c) 70 90 111 a discharge current (v cskip = 1.25 v) i cskip(d) 6.5 8.6 11 a number of pulses to exit cycle skip mode pulse cskip ? 3 ? ? upper threshold voltage (ramp up v cskip , v cs = 1.0 v) v cskip(peak) 2.83 3.03 3.24 v lower threshold voltage (ramp down v cskip ) v cskip(valley) 0.39 0.465 0.52 v threshold v oltage hysteresis v cskip(h) ? 2.5 ? v 5.0 v reference output voltage (i ref = 0 ma) v ref 4.9 5.0 5.1 v load regulation (i ref = 0 to 5.0 ma) v ref(load) ? 16 50 mv line regulation (v aux = 7.5 to 20 v, i ref = 0 ma) v ref(line) ? 10 50 mv discharge current (v uvov = 0 v, v ref = 2.5 v) i ref(d) 3.8 ? ? ma oscillator frequency t j = 25 c t j = ? 40 c to 125 c f osc 222 211.2 246 ? 272.2 277.2 khz peak v oltage v rtct(peak) ? 2.95 ? v valley voltage v rtct(valley) ? 2.1 ? v discharge current (v rtct = 2.3 v) i rtct ? 490 ? a maximum operating frequency (note 4) f max 1.0 ? ? mhz duty cycle (r d = 25 k ) d 58.5 62.0 64.7 % adjustable maximum duty cycle (note 4) d max 85 ? ? % 4. guaranteed by design only.
NCP1562A, ncp1562b http://onsemi.com 8 electrical characteristics (continued) (v in = 48 v, v aux = 12 v, v uvov = 2.3 v, v ea = open, v cskip = 0 v, v cs = 0 v, v ss = open, r t = 13.3 k , c aux = 10 f, c t = 470 pf, c out1 = c out2 = 100 pf, c uvov = 0.01 f, c cskip = 6800 pf, r d = 25 k , r sync = 5.0 k , c ref = 0.1 f, r ff = 29.4 k , c ff = 470 pf. for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted.) characteristic symbol min typ max unit synchronization output pulse width t o(sync) 70 110 ? ns output voltage high (r sync = ) v h(sync) ? 4.3 ? v sync threshold voltage (note 5) v sync 3.5 ? ? v sync input pulse width (v sync = 3.5 v) t sync ? ? t o(sync)min ns maximum sync frequency (note 5) f sync ? ? 1.0 mhz source current (note 5) i sync(d) ? 1.0 ? ma soft ? start/stop charge current (v ss = 1.6 v) i ss(c) 8.3 10.2 13.1 a discharge current (v uvov = 0 v, v ss = 1.6 v) i ss(d) 72 95 115 a soft ? stop reset voltage (v ff = 0 v) v reset(ss) ? 115 ? mv outputs overlap time delay (tested at 50% of w aveform) leading trailing t d(leading) t d(trailing) 37 72 45 90 ? ? ns output voltage (i out = 0 ma, note 5) low state high state v ol v oh ? 11.8 ? ? 0.25 ? v drive resistance (ft only) out1 sink (v rtct = 4.0 v, v out1 = 1.0 v) t j = 25 c t j = ?40 c to 125 c out1 source (v rtct = 2.5 v, v out1 = 11 v) t j = 25 c t j = ?40 c to 125 c out2 sink (v rtct = 4.0 v, v out2 = 1.0 v) t j = 25 c t j = ?40 c to 125 c out2 source (v rtct = 2.5 v, v out2 = 11 v) t j = 25 c t j = ?40 c to 125 c r snk1 r src1 r snk2 r src2 ? ? ? ? ? ? ? ? 2.8 ? 4.7 ? 11.4 ? 11.6 ? 3.6 5.03 5.75 7.45 12.7 20.0 13.5 20.0 rise time (10% to 90%, c out1 = 2200 pf, c out2 = 220 pf) out1 out2 t r1 t r2 ? ? 26 19 ? ? ns fall time (90% to 10%, c out1 = 2200 pf, c out2 = 220 pf) out1 out2 t f1 t f2 ? ? 10 10 ? ? ns pwm comparator input resistance r in(vea) 14 25 50 k lower input threshold v ea(l) 0.48 0.83 1.04 v delay to output (from v oh to 0.5 v oh ) t pwm ? 100 ? ns 5. guaranteed by design only.
NCP1562A, ncp1562b http://onsemi.com 9 v inhibit , inhibit threshold voltage (v) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 2. startup circuit inhibit v oltage threshold vs. junction temperature v aux , auxiliary supply voltage (v) 11.0 6.0 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 3. auxiliary supply voltage thresholds vs. junction temperature 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 v aux(on) i start , startup current (ma) 12 2 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 4. startup current vs. junction temperature 11 10 9 8 7 6 5 4 3 v aux = v inhibit + 0.2 v v aux = v aux(on) ? 0.2 v v in = 48 v i start , startup current (ma) 4 10 9 8 7 6 5 2 4 6 8 10 12 v aux , supply voltage (v) figure 5. startup c urrent vs. supply voltage v in = 48 v t j = 25 c i start(off) , startup circuit leakage current ( a) 100 10 200 175 150 125 100 75 50 25 0 v in , input voltage (v) figure 6. startup circuit leakage current vs. input voltage 90 80 70 60 50 40 30 20 v aux = 12 v 0 t j = 25 c t j = ? 40 c t j = 125 c 0 3 2 1 0 v aux(off1) v aux(off2)
NCP1562A, ncp1562b http://onsemi.com 10 undervoltage overvoltage i aux , auxiliary supply current (ma) 10 1 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 7. auxiliary supply current vs. junction temperature 9 8 7 6 5 4 3 2 v uvov = 2.3 v, c out1 = c out2 = 100 pf v aux = 12 v 0 v uvov = 2.3 v, v ea = 0 v v uvov = 0 v i aux3 , power supply current (ma) 8.0 3.5 15 14 13 12 11 10 v aux , power supply voltage (v) figure 8. supply current vs. supply voltage 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.0 20 v in = 48 v t j = 25 c f osc 230 khz c out1 = c out2 = 100 pf t j , junction temperature ( c) v uv/ov , line under/overvoltage thresholds (v) 3.2 2.2 ? 50 3.1 3.0 2.9 2.8 2.7 2.5 2.4 2.3 2.0 2.6 2.1 ? 25 0 25 50 75 100 125 150 figure 9. line under/overvoltage thresholds vs. junction temperature v uv/ov(h) , under/overvoltage hysteresis (mv) 150 50 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 10. line under/overvoltage hysteresis vs. junction temperature 140 130 120 110 100 90 80 70 60 undervoltage overvoltage i offset(uvov) , uvov offset current ( a) 75 25 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 11. uvov offset current vs. junction temperature 70 65 60 55 50 45 40 35 30 v aux = 12 v v uvov = 2.8 v i ff(d) , discharge current (ma) 50 0 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 12. ff discharge current vs. junction temperature 45 40 35 30 25 20 15 10 5 v cc = 12 v v ss = 0 v v ff = 0.5 v 16 18 17 19
NCP1562A, ncp1562b http://onsemi.com 11 ncp1562b NCP1562A v ff(peak) , ff peak voltage (v) 3.5 2.5 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 13. ff offset and ss reset voltages vs. junction temperature 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 v ilim , current limit threshold voltage (mv) 550 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 14. feedforward peak voltage vs. junction temperature 500 450 400 350 300 250 200 150 v offset(ff) /v reset(ss) , ff offset and ss reset voltages (mv) 250 0 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) 225 200 175 150 125 100 75 50 25 ff ? offset ss reset figure 15. current limit threshold voltage vs. junction temperature t ilim , current limit propagation delay (ns) 150 50 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 16. current limit propagation delay vs. junction temperature 140 130 120 110 100 90 80 70 60 t leb , leb time (ns) 100 0 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 17. leading edge blanking time vs. junction temperature 90 80 70 60 50 40 30 20 10
NCP1562A, ncp1562b http://onsemi.com 12 i ref(d) , v ref discharge current (ma) 10 0 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 18. cycle skip charge current vs. junction temperature 9 8 7 6 5 4 3 2 1 v cc = 12 v v uvov = 0 v v ref = 2.5 v v cskip(peak) , upper threshold (v) 3.5 2.5 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 upper threshold v cskip(valley) , lower threshold (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 lower threshold v ref , reference voltage (v) 5.25 4.75 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 19. cycle skip discharge current vs. junction temperature 5.20 5.15 5.10 5.05 5.00 4.95 4.90 4.85 4.80 v aux = 12 v v ref = 0 ma v ref = 5 ma i cskip(c) , cycle skip charge current ( a) 150 50 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) 140 130 120 110 100 90 80 70 60 v cskip = 1.25 v figure 20. cycle skip voltage thresholds vs. junction temperature f osc , oscillat or frequency (khz) 750 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 21. reference voltage vs. junction temperature v aux = 12 v r t = 14 k r d = 69.8 k 650 550 500 450 400 350 300 250 200 600 c t = 150 pf c t = 470 pf c t = 220 pf figure 22. v ref discharge current vs. junction temperature 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) v cskip = 1.25 v i cskip(d) , cycle skip discharge current ( a) 15 14 13 12 11 10 9 8 7 6 5 figure 23. oscillator frequency vs. junction temperature 700
NCP1562A, ncp1562b http://onsemi.com 13 t d(trail) t d(lead) t d(trail) t d(lead) t d(trail) t d(lead) d, duty cycle (%) 90 30 10 r t , timing resistor (k ) 85 75 70 65 60 55 50 45 40 80 50 70 90 110 v aux = 12 v t j = 25 c r d = 69.8 k c t = 150 pf c t = 220 pf c t = 470 pf d, duty cycle (%) 90 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 24. oscillator frequency vs. timing resistor v aux = 12 v r d = 69.8 k 85 75 70 65 60 55 50 45 40 80 r t = 15.8 k , c t = 220 pf r t = 11.8 k , c t = 470 pf r t = 20 k , c t = 150 pf i ss(c) , charge current ( a) 15 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) v aux = 12 v 14 12 11 10 9 8 7 6 5 13 discharge (v uvov = 0 v) charge i ss(d) , discharge current ( a) t d , overlap time delay (ns) 500 80 0 r d , delay resistor (k ) figure 25. duty cycle vs. timing resistor 450 350 300 250 200 150 100 50 0 400 160 240 320 400 v aux = 12 v t j = 25 c leading trailing 150 140 130 120 110 100 90 80 70 60 50 t d , overlap time delay (ns) 400 figure 26. duty cycle vs. junction temperature 350 250 200 150 100 50 0 300 v aux = 12 v t j , junction temperature ( c) 150 125 100 75 50 25 0 ? 25 ? 50 f osc , oscillat or frequency (khz) 30 10 r t , timing resistor (k ) 800 700 600 500 400 300 200 100 900 50 70 90 110 v aux = 12 v t j = 25 c c t = 150 pf c t = 220 pf c t = 470 pf figure 27. soft ? start/stop charge and discharge currents vs. junction temperature figure 28. overlap time delay vs. delay resistor figure 29. overlap time delay vs. junction temperature r d = 200 k r d = 20 k r d = 69.8 k 0
NCP1562A, ncp1562b http://onsemi.com 14 sink, v out2 = 1 v source, v out2 = 11 v r snk/src , output 2 drive resistance ( ) 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) v aux = 12 v 17 16 15 14 13 12 11 6 18 r in(vea) , v ea input resistance (k ) 50 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) 45 35 30 25 20 15 10 5 0 40 v ea(l) , pwm comparator lower input threshold (v) 1.5 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) 1.4 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 1.3 r snk/src , output 1 drive resistance ( ) 10 150 125 100 75 50 25 0 ? 25 ? 50 t j , junction temperature ( c) figure 30. output 1 drive resistance vs. junction temperature v aux = 12 v 9 7 6 5 4 3 2 1 0 8 sink, v out1 = 1 v source, v out1 = 11 v figure 31. output 2 drive resistance vs. junction temperature figure 32. v ea input resistance vs. junction temperature figure 33. pwm comparator lower input threshold vs. junction temperature v ea = 0 v 10 9 8 7
NCP1562A, ncp1562b http://onsemi.com 15 detailed operating description the ncp1562x is a family of voltage mode controllers designed for dc ? dc converters requiring high ? efficiency and low parts count. these controllers incorporate two in phase outputs with an adjustable overlap delay. the main output is designed for driving a forward converter primary mosfet. the secondary output is designed for driving an active clamp circuit mosfet, a synchronous rectifier on the secondary side, or an asymmetric half bridge circuit. two distinctive features of the ncp1562 are the soft ? stop and a cycle skip overcurrent detector with a time threshold. the soft ? stop powers down the converter in a controlled manner after a fault is detected. the cycle skip timer disables the converter if a continuous overcurrent condition is present. the ncp1562 reduces component count and system size by incorporating high accuracy on critical specifications such as programmable maximum duty cycle, undervoltage detector and overcurrent threshold. additional features found in the ncp1562 include line feedforward, bidirectional frequency synchronization up to 1.0 mhz, cycle ? by ? cycle current limit with leading edge blanking (leb), independent under and overvoltage detectors, internal startup circuit and soft ? start. soft ? stop and soft ? start the ncp1562 incorporates a novel soft ? stop and soft ? start architecture that combines soft ? start and soft ? stop functions on a single pin. soft ? stop reduces the duty cycle until it reaches 0% once a fault is detected. by slowly reducing the duty cycle during power down, the active clamp capacitor (c clamp ) is discharged. this prevents oscillations between the power transformer and c clamp , and ensures the converter turns off in a predictable state. soft ? start slowly increases the duty cycle during power up allowing the controller to gradually reach steady state operation. combined, both features reduce system stress and power surges. the duty cycle is controlled by comparing the ss capacitor voltage (v ss ) to the feedforward (ff) ramp. soft ? start or soft ? stop is implemented by slowly charging or discharging the capacitor on the ss pin. out1 is disabled once the ff ramp exceeds v ss . the soft ? start charge current is 10 a and the soft ? stop dischar ge current is 100 a, guaranteeing a faster turn off time. the converter enters a soft ? stop sequence if an undervoltage, overvoltage, cycle skip or thermal shutdown condition is detected. once the converter enters the soft ? stop mode, it will stay in soft ? stop mode until v ss reaches 0.2 v even if the fault is removed prior to reaching 0.2 v. the preset 1:10 char ge:discharge ratio can be reduced by placing an external resistor between the v ref and ss pins. the resistor should be sized such that the total charge current does not exceed 100 a. otherwise the converter will not be able to complete a soft ? stop sequence. depending on the converter state, a soft ? stop sequence is handled differently to ensure the fastest response time and prevent system malfunction. if a soft ? stop sequence starts before v ss exceeds the maximum voltage clamp of the ff ramp (typ. 3.0 v) and the pwm comparator (v ea ) is not yet controlling the duty cycle, a controlled discharge of c ss commences immediately, as shown in figure 34. however, if v ea is controlling the duty cycle, c ss is discharged until soft ? stop sets a duty cycle equal to the duty cycle set by v ea . a controlled discharge commences afterwards, as shown in figure 35. if v ss exceeds the ff ramp and the v ea is not controlling the duty cycle, v ss is forced to the peak voltage of the ff ramp, before starting a controlled discharge of c ss , as shown in figure 36. the duty cycle set at the beginning of the soft ? stop event never exceeds the duty cycle prior to the soft ? stop event. figure 34. soft ? stop before soft ? start is complete and v ea is open. (v ea is not controlling the duty cycle) v ea v ss ff ramp figure 35. soft ? stop behavior when v ea controls the duty cycle. v ss v x = v ea ? v f v ea
NCP1562A, ncp1562b http://onsemi.com 16 figure 36. soft ? stop behavior after soft ? start is complete and v ea is open. (v ea is not controlling the duty cycle) v ea ff ramp v ss if the voltage on the v aux pin reaches v aux(off2) , c ss is immediately discharged and the outputs are disabled. v ss should not be pulled up or down externally. current limit the ncp1562 has two overcurrent modes, cycle ? by ? cycle and cycle skip, providing the best protection during momentary and continuous overcurrent conditions. cycle ? by ? cycle in cycle ? by ? cycle, the conduction period ends once the voltage on the cs pin reaches the current limit voltage threshold (v ilim ). the NCP1562A has a v ilim of 0.2 v and the ncp1562b has a v ilim of 0.5 v. cycle skip traditionally, a voltage on the cs higher than v ilim has been used to trigger a cycle skip fault. unfortunately, the fast response time of modern controllers makes it hard to reach a voltage on the cs pin higher than v ilim . instead of using a higher voltage threshold to detect a cycle skip fault, the ncp1562 uses a timer. it monitors the current limit comparator and if a continuous cycle ? by ? cycle current limit condition exists the converter is disabled. the time to disable the converter and the time the converter is disabled are programmed by the capacitor on the cskip pin, c cskip . the cycle skip detection circuit charges c cskip with a continuous 100 a current once cycle ? by ? cycle current limit fault is detected. if the current limit fault persists, c cskip continues to charge until reaching the cycle skip upper threshold (v cskip(peak) ) of 3.0 v. once reached, the converter enters the soft?stop mode and c cskip is discharged with a constant 10 a current. a new soft ? start sequence commences once c cskip reaches the lower cycle skip threshold (v cskip(valley) ) of 0.5 v. if the overcurrent condition is still present, the capacitor starts charging on the next current limit event. otherwise, c cskip is discharged down to 0 v. the cycle skip capacitor provides a means of remembering previous overcurrent conditions. if a continuous overcurrent condition is removed before reaching v cskip(peak) , c cskip starts a controlled discharge. if the continuous overcurrent fault is once again detected before c cskip is completely discharged, c cskip charges from its existing voltage level, taking less time to reach v cskip(peak) . figure 37 shows operating waveforms during a continuous overcurrent condition. for optimal operation, the cycle skip discharge time should be longer than the soft ? stop period. figure 37. cycle skip waveforms v cskip(valley) v cskip(peak) v cskip cs v ilim v ss
NCP1562A, ncp1562b http://onsemi.com 17 in some instances it may be desired to latch (instead of auto re ? start) the ncp1562 after a cycle skip event is detected. this can be easily achieved by adding an external latch. figures 35 and 36 show an implementation of an integrated and a discrete latch, respectively. in general the circuits work by pulling cskip to v ref , preventing it from reaching v cskip(valley) once the cskip voltage reaches the turn on threshold of the latch. the external latch is cleared by bringing the uvov voltage below v uv and disabling v ref . v ref c ref cskip c cskip outy v cc ina oe mc74vhc1gt126 figure 38. external latch implemented using on semiconductor?s minigate buffer the latch in figure 38 consists of a ttl level tri ? state output buffer from on semiconductor?s minigate family. the enable (oe) and output (outy) terminals are connected to cskip and the v cc and ina pins are connected to v ref . the output of the buffer is in a high impedance mode when oe is low. once a continuous current limit condition is detected, the cskip timer is enabled and cskip begins charging. once the voltage on cskip reaches the enable threshold of the buffer, the output of the buffer is pulled to v ref , latching the cskip timer. the oe threshold of the buffer is typically 1.5 v. v ref c ref c cskip cskip bss84l m2 24.9 k 2n7002l r pull ? up m1 figure 39. external latch implemented using discrete n and p ? channel mosfets a latch implemented using discrete n and p ? channel mosfets is sh own in figure 39. the latch is enabled once the cskip voltage reaches the threshold of m1. once m1 turns on, it pulls low the gate of m2. cskip is then pulled to v ref by m2. it is important to size r pull ? up correctly. if r pull ? up is too big, it will not keep m2 off while v ref charges. this will cause the controller to latch during initial power ? up. in this particular implementation the turn on threshold of m1 is 2 v and r pull ? up is sized to 24.9 k . leading edge blanking the current sense signal is prone to leading edge spikes caused by the power switch transitions. the current signal is usually filtered using an rc low?pass filter to avoid premature triggering of the current limit circuit. however, the low pass filter will inevitably change the shape of the current pulse and also add cost and complexity. the ncp1562 uses leb circuitry that blocks out the first 70 ns (typ) of each current pulse. this removes the leading edge spikes without altering the current waveform. the blanking period is disabled during soft ? start as the blanking period may be longer than the startup duty cycle. it is also disabled if the output of the saturation comparator is low , indicating that the output is not yet in regulation. this occurs during power up or during an output overload condition. supply voltage and startup circuit the ncp1562 internal startup regulator eliminates the need for external startup components. in addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. the ncp1562 incorporates an optimized startup circuit that reduces the requirement of the supply capacitor, particularly important in size constrained applications. the startup regulator consists of a constant current source that supplies current from the input line voltage (v in ) to the supply capacitor on the v aux pin (c aux ). the startup current (i start ) is typically 10 ma. once c aux is charged to 10.3 v (v aux(on) ), the startup regulator is disabled and the outputs are enabled if there are no uv, ov, cycle skip or thermal shutdown faults. the startup regulator remains disabled until the lower voltage threshold (v aux(off1) ) of 8.0 v is reached. once reached, the startup circuit is enabled. if the bias current requirement out of c aux is greater than the startup current, v aux will discharge until reaching the lower voltage threshold (v aux(off2) ) of 7.0 v. upon reaching v aux(off2) , the outputs are disabled. once the outputs are disabled, the bias current of the ic is reduced, allowing v aux to charge back up. this mode of operation allows a dramatic reduction in the size of c aux as not all the power required for startup needs to be stored by c aux . this mode of operation is known as dynamic self supply (dss). figure 40 shows the relationship between v aux(on) , v aux(off1) , v aux(off2) and uv. as shown in figure 40, the outputs are not enabled until the uv fault is removed and v aux reaches v aux(on) .
NCP1562A, ncp1562b http://onsemi.com 18 figure 40. startup circuit waveforms v aux(off1) v aux(on) v aux v inhibit v uvov v ref v ss v out1 the startup regulator is disabled by biasing v aux above v aux(on) . this feature allows the ncp1562 to operate from an independent 12 v supply. if operating from an independent supply, the v in and v aux pins should be connected together. the independent supply should maintain v aux above v aux(on) . otherwise, the output latch will not be set and the outputs will remain off after a fault condition is removed. the startup circuit sources current into the v aux pin. it is recommended to place a diode between c aux and the auxiliary supply as shown in figure 41. this allows the ncp1562 to charge c aux while preventing the startup regulator from sourcing current into the auxiliary supply. disable v in i start v aux i aux c aux i supply auxiliary supply or independent supply figure 41. recommended v aux configuration c aux provides power to the controller while operating in the self ? bias or dss mode. during the converter powerup, c aux must be sized such that a v aux voltage greater than v aux(off2) is maintained while the auxiliary supply voltage is building up. otherwise, v aux will collapse and the controller will turn off. also, the v aux discharge time (from 10.3 v to 7.0 v) must be greater that the soft ? start charge period to assure the converter turns on. the ic bias current, gate charge load on the outputs, and the 5.0 v reference load must be considered to correctly size c aux . the current consumption due to external gate charge is calculated using equation 1. i aux(gate charge) f q g (eq. 1) where, f is the operating frequency and q g is the gate charge. an internal supervisory circuit monitors v aux and prevents excessive power dissipation if the v aux pin is accidentally shorted. while v aux is below 1.2 v, the startup circuit is disabled and a current source (i inhibit ) charges v aux with a minimum current of 50 a. once v aux reaches 1.2 v the startup circuit is enabled. therefore it is imperative that v aux is not loaded (driver, resistor divider, etc.) with more than 50 a while v aux is below 1.2 v. otherwise, v aux will not charge. if a load greater than 50 a is present, a resistor can be placed between the v in and v aux pins to help charge v aux to 1.2 v. the startup circuit is rated at a maximum voltage of 100 v. if the device operates in the dss mode, power dissipation should be controlled to avoid exceeding the maximum power dissipation of the controller. if dissipation on the controller is excessive, a resistor can be placed in series with the v in pin. this will reduce power dissipation on the controller and transfer it to the series resistor. line under/overvoltage detector the same pin is used for both line undervoltage (uv) and overvoltage (ov) detection using a novel architecture
NCP1562A, ncp1562b http://onsemi.com 19 (patent pending). this architecture allows both the uv and ov levels to be set independently. both the uv and ov detectors have a 100 mv hysteresis. the line voltage is sampled using a resistor divider as shown in figure 42. ? + ov comparator v ovcomp 3.0 v + ? ? + uv comparator v uvcomp 2.0 v + ? ? + 2.5 v + ? uvov c uvov r1 r2 v in i offset(uvov) figure 42. line uvov detectors a uv condition exists if the uvov voltage is below v uv , typically 2.0 v. the ratio of r1 and r2 determines the uv turn threshold. once the uvov voltage exceeds 2.5 v, an internal current source (i offset(uvov) ) sinks 50 a into the uvov pin. this will clamp the uvov voltage at 2.5 v while the current across r1 is less than i offset(uvov) . if the input voltage continues to increase, the 50 a source will be overridden and the voltage at the uvov pin will increase. an ov condition exists if the uvov voltage exceeds v ov , typically 3.0 v. figure 43 shows the relationship between uvov and v in . figure 43. uvov detectors typical waveforms time v uvov (v) v in (v) v ovcomp v uvcomp v uvov while the internal current source is disabled, the uvov voltage is solely determined by the ratio of r1 and r2. the input voltage at which the converter turns on is given by equation 1. once the internal current source is enabled, the absolute value of r1 together with the ratio of r1 and r2 determine the turn off threshold as shown in equation 2. v in(uv) v uv (r 1 r 2 ) r 2 (eq. 1) v in(ov) v ov (r 1 r 2 ) r 2 (i offset(uvov) r1) (eq. 2) the undervoltage threshold is trimmed during manufacturing to obtain 3% accuracy allowing a tighter power stage design. once the line voltage is within the operating range, and v aux reaches v aux(on) , the outputs are enabled and a soft ? start sequence commences. if a uv or ov fault is detected afterwards, the converter enters a soft ? stop mode. a small capacitor is required (>1000 pf) from the uvov pin to gnd to prevent oscillation of the uvov pin and filter line transients. line feedforward the ncp1562 incorporates line feedforward (ff) to limit the maximum volt ? second product. it is the line voltage times the on time. this limit prevent saturation of the transformer in forward and flyback topologies. another advantage of feedforward is a controller frequency gain independent of line voltage. a constant gain facilitates frequency compensation of the converter. feedforward is implemented by generating a ramp proportional to v in and comparing it to the error signal. the error signal solely controls the duty cycle while the input voltage is fixed. if the line voltage changes, the ff ramp slope changes and duty cycle is immediately adjusted instead of waiting for the change to propagate around the feedback loop and be reflected back on the error signal. the ff ramp is generated with an r ? c (r ff c ff ) divider from the input line as shown in figure 44. the divider is selected such that the ff ramp reaches 3.0 v in the desired maximum on time. the ff ramp terminates by effectively grounding c ff during the converter off time. this can be triggered by the ff ramp reaching 3.0 v, or any other condition that limits the duty cycle. to pwm and vs comparators ff reset i ff(d) v in r ff i rff c ff ff 3 v 0 v t t on figure 44. feed forward ramp generation the ff pin is effectively grounded during power or during standby mode to prevent the ff pin from charging up to v in .
NCP1562A, ncp1562b http://onsemi.com 20 the minimum value of r ff is determined by the ff ramp discharge current (i ff(d) ). the current through r ff (i rff ) should be at least ten times smaller than i ff(d) for a sharp ff ramp transition. equations 3 and 4 are used to determine r ff and c ff . v in 10 i ff(d) r ff (eq. 3) c ff d ln
v in v in ? 3v f r ff (eq. 4) where, f is the operating frequency. it is recommended to bias the ff circuit with enough current to provide good noise immunity. pwm comparator in steady state operation, the pwm comparator adjusts the duty cycle by comparing the error signal to the ff ramp. the error signal is fed into the v ea pin. the v ea pin can be driven directly with an optocoupler without the need of an external pullup resistor as shown in figure 45. in some instances, it may be required to have a pullup resistor smaller than the internal resistor (r4) to adjust the gain of the isolation stage. this is easily accomplished by connecting an external resistor (r ea ) in parallel with r4. r ea is connected between the v ref and v ea pins. the effective pullup resistance is the parallel combination of r4 and r ea . pwm comparator + ? + ? 0.2 v 270 k 2 k v ref r ea (optional) v ea ff feedback signal ff ramp 3 v 0 v figure 45. optocoupler driving v ea input 20 k the drive of the v ea pin is simplified by internally incorporating a series diode and resistor. the series diode provides a 0.7 v offset between the v ea input and the pwm comparator inverting input. it allows reaching zero duty cycle without the need of pulling the v ea pin all the way to gnd. the outputs are enabled if the v ea voltage is approximately 0.5 v above the valley of the ff ramp. outputs the ncp1562 has two in ? phase output drivers with an adjustable overlap delay (t d ). the main output, out1, has a source resistance of 4.0 (typ) and a sink resistance of 2.5 (typ). the secondary output, out2, has a source and a sink resistance of 12 (typ). out1 is rated at a maximum of 2.0 a and out2 is rated at a maximum of 1.0 a. if a higher drive capability is required, an external driver stage can be easily added as shown in figure 46. v aux output figure 46. discrete boost drive stage out1 or out2 out1 driv es the main mosfet, and out2 drives a low side p ? channel active clamp mosfet. a high side n ? channel active clamp mosfet or a synchronous rectifier can also be driven by inverting out2. out2 is purposely sized smaller than out1 because the active clamp mosfet only sees the magnetizing current. therefore, a smaller active clamp mosfet with less input capacitance can be used compared to the main switch. once v aux reaches v aux(on) (typically 10.3 v), the internal startup circuit is disabled and the outputs are enabled if no faults are present. otherwise, the outputs remain disabled until the fault is removed and v aux reaches v aux(on) . the outputs are disabled after a soft ? stop sequence if v aux is below v aux(on) or if v aux reaches 7.0 v. the outputs are biased directly from v aux and their high state voltage is approximately v aux . therefore, the auxiliary supply voltage should not exceed the maximum gate voltage of the main or active clamp mosfet. the high current drive capability of the outputs will generate inductance ? induced spikes if inductance is not reduced on the outputs. this can be done by reducing the connection length between the drivers and their loads and using wide connections. overlap delay the overlap delay prevents simultaneous conduction of the main and active clamp mosfets. the secondary output, out2, precedes out1 during a low to high transition and trails out1 during a high to low transition. figure 47 shows the relationship between out1 and out2. t d (leading) out1 out2 t d (trailing) figure 47. output timing diagram
NCP1562A, ncp1562b http://onsemi.com 21 the output overlap delay is adjusted by connecting a resistor, r d , from the t d pin to ground . the overlap delay is proportional to r d . a minimum delay of 20 ns is obtained by grounding the t d pin. the leading delay is purposely made longer than the trailing delay. this allows the user to optimize the delay for the turn on transition of the main switch and ensures the active clamp switch always exhibits zero volt switching. analog and power ground (pgnd) the ncp1562 has an analog ground, gnd, and a power ground, pgnd, terminal. gnd is used for analog connections such as v ref , r t c t , feedforward among others. pgnd is used for high current connections such as the internal output drivers. it is recommended to have independent analog and power ground planes and connect them at a single point, preferably at the ground terminal of the system. this will prevent high current flowing on pgnd from injecting noise in gnd. the pgnd connection should be as short and wide as possible to reduce inductance ? induced spikes. oscillator the oscillator frequency and maximum duty cycle are set by an r t c t divider from v ref as shown in figure 48. a 500 a current source (i rtct ) discharges the timing capacitor (c t ) upon reaching its peak threshold (v rtct(peak) ), typically 3.0 v. once c t reaches its valley voltage (v rtct(valley) ), typically 2.0 v, i rtct turns off allowing c t to charge back up through r t . the resulting waveform on the rtct pin has a sawtooth like shape. enable i rtct v ref rtct r t c t 3 v 2 v figure 48. oscillator configuration out2 is set high once v rtct(valley) is reached, followed by out1 delayed by the overlap delay. once v rtct(peak) is reached, out1 goes low, followed by out2 delayed by t d . the duty cycle is the c t charge time (t rtct(c) ) minus the overlap delay over the total charge and discharge (t rtct(d) ) times. the charge and discharge times are calculated using equations 5 and 6. however, these equations are an approximation as they do not take into account the propagation delays of the internal comparator. t rtct(c) r t c t ln
v rtct(valley) ? v ref v rtct(peak) ? v ref (eq. 5) t rtct(d) r t c t ln
(i rtct r t ) v rtct(peak) ? v ref (i rtct r t ) v rtct(valley) ? v ref (eq. 6) the duty cycle, d, is given by equation 7. d t rtct(c) ? t d t rtct(c) t rtct(d) (eq. 7) substituting equations 5, 6, and 7, and after a little algebraic manipulation and replacing values, it simplifies to: d ln
v rtct(valley) ? v ref v rtct(peak) ? v ref ? t d r t c t ln
v rtct(valley) ? v ref v rtct(peak) ? v ref (i rtct r t ) v rtct(peak) ? v ref (i rtct v rtct(valley) ? v ref (eq. 8) it can be observed that d is set by r t , c t and t d . this equation has two variables and can be solved iteratively. in general, the time delay is a small portion of the on time and can be ignored as a first approximation. r t is then selected to achieve a given duty cycle. once the r t is selected, c t is chosen to obtain the desired operating frequency using equation 9. f 1 r t c t ln
v rtct(valley) ? v ref v rtct(peak) ? v ref (i rtct r t ) v rtct(peak) ? v ref (i rtct r t ) v rtct(valley) ? v ref (eq. 9) figures 23 through 26 show the frequency and duty cycle variation vs r t for several c t values. r t should not be less than 6.0 k . otherwise, the r t c t charge current will exceed the pulldown current and the oscillator will be in an undefined state. synchronization a proprietary bidirectional frequency synchronization architecture allows multiple ncp1562 to synchronize in a master ? slave configuration. it can synchronize to frequencies above or below the free running frequency.
NCP1562A, ncp1562b http://onsemi.com 22 the sync pin is in a high impedance mode during the charging of the rtct ramp. in this period the oscillator accepts an external sync pulse. if no pulse is detected upon re aching the peak of the rtct ramp, a 100 ns sync pulse is generated. the sync pulse is generated by internally pulling the sync pin to v ref . the peak voltage of the sync pin is typically 4.3 v. once the 100 ns timer expires, the pin goes back into a high impedance mode and an external resistor is required for pulldown as shown in figure 49. v ref rtct sync r sync c t r t figure 49. sync pulse the slew rate of the sync pin is determined by the pin capacitance and external pulldown resistor. the maximum source current of the sync pin is 1.0 ma. the resistor is sized to allow the sync pin to discharge before the start of the next cycle. if an external pulse is received on the sync pin before the internal pulse is generated, the controller enters the slave mode of operation. once operation in slave mode commences, c t begins discharging and the r t c t ramp upper threshold is increased to 4.0 v. if a controller in slave mode does not receive a sync pulse before reaching the r t c t ramp peak voltage (4.0 v), the upper threshold is reset back to 3.0 v and the converter reverts to operation in master mode. to guarantee the converter stays in slave mode, the minimum clock period of the master controller has to be less than the r t c t charge time from 2.0 v to 4.0 v. two ncp1562?s are synchronized by connecting their sync pins together. the first device that generates a sync pulse during powerup becomes the master. a diode connected as shown in figure 50 can be used to permanently set one controller as the master. the diode prevents the master from receiving the sync pulse of the slave controller. master controller slave controller sync r sync1 r sync2 sync figure 50. master ? slave configuration 5.0 v reference the ncp1562 has a precision 5.0 v reference output. it is a buffered version of the internal reference. the 5.0 v reference is biased directly from v aux and it can supply up to 5.0 ma. load regulation is 50 mv and line regulation is 100 mv within the specified operating range. it is required to bypass the reference with a capacitor. the capacitor is used for compensation of the internal regulator and high frequency noise filtering. the capacitor should be placed across the v ref and gnd pins. in most applications a 0.1 f will suffice. a bigger capacitor may be required to reduce the voltage ripple caused by the oscillator current. the recommended capacitor range is between 0.047 f and 1.0 f. during powerup, the 5.0 v reference is enabled once v aux reaches v aux(on) and a uv fault is not present. otherwise, the reference is enabled once the uv fault is removed and v aux reaches v aux(on) . once a uv fault is detected after the reference has been enabled, the reference is disabled after the soft ? stop sequence is complete if the uv fault is still present. if the uv fault is removed before soft ? stop is complete, the reference is not disabled. application information on semiconductor provides an electronic design tool, a demonstration board and an application note to facilitate design of the ncp1562 and reduce development cycle time. all the tools can be downloaded or ordered at www.onsemi.com. the electronic design tool allows the user to easily determine most of the system parameters of an active clamp forward converter. the tool evaluates the power and active clamp stages as well as the frequency response of the system. the tool is used to design a converter for a 48 v telecom system. the converter delivers 100 w at 3.3 v. the circuit schematic is shown in figure 51. the converter design is described in application note and8273/d.
NCP1562A, ncp1562b http://onsemi.com 23 uvov ff cs gnd rtct sync vref vin out1 pgnd out2 cskip td ss vaux vea j1 j2 j5 l3 c22 + 47 1 c10 d7 d2 2 1 4t tx1 51665 1000 1.5 l1 c2 c1 2.2 c3 r1 523 k c16 0.01 r4 32.4 k v ref c23 0.1 d1 r15 4.75 4 x2 r17 10 k d4 35 m r2 c14 0.018 44.2 k r5 c28 0.1 0.01 c13 c11 100 p r16 10 k x1 c26 0.01 r3 45.3 k 4 7 r23 2.0 x3 x4 r11 4.22 k r6 10 k q1 1 2 3 c8 0.1 c12 270 p 27 p c30 r8 32.4k 15 k r9 cs c24 470 p r10 100 u2 ps2703?i?m?a 1 2 r18 3.01 k bc817 r25 10 k x5 x6 4 4 sec_pwr1 l2 1.5 + + c17 47 c18 47 c19 150 c20 150 ? + 7 u4b 5 6 348 r13 r14 953 ? + 4 8 1 u4a 3 2 sec_pwr2 sec_pwr1 q2 bc807 c15 2.2 24.9 r26 d6 d3 49.9 r12 4.22 k r7 c9 0.1 c6 0.1 2.49 k r28 4.22 k r27 5 3 4 c5 1000 p r22 open r21 16.2 k c29 1000 p d5 5.9 k r20 c25 0.056 j3 j4 r30 348 8 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 cs 6t 1t 4 3 c27 2200 p lm258g 3 4 2 1 3 NCP1562A 4 4 u1 figure 51. circuit schematic c31 47 5,6,7,8 1,2,3 5,6,7,8 5,6,7,8 1,2,3 1,2,3 1,2,3 1,2,3 5,6,7,8 5,6,7,8 3.3 v + ? r24 10 k r29 2.0 36?72 v + ? 2.2 2.2 sec_pwr2 + c4 2.2 c7 22 r19 10 + c21 150 d1 = mbrm120et1g d2?d7 = mmsd914t1g x1 = fdd2582 x2 = irf6217pbf x3?x6 = ntmfs4835nt1g
NCP1562A, ncp1562b http://onsemi.com 24 ordering information device package current limit shipping ? NCP1562Adbr2g tssop ? 16 (pb ? free) 200 mv 2500 tape & reel ncp1562bdbr2g tssop ? 16 (pb ? free) 500 mv 2500 tape & reel NCP1562Adr2g so ? 16 (pb ? free) 200 mv 2500 tape & reel ncp1562bdr2g so ? 16 (pb ? free) 500 mv 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d.
NCP1562A, ncp1562b http://onsemi.com 25 package dimensions tssop ? 16 dt suffix case 948f ? 01 issue a ?? ?? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n
NCP1562A, ncp1562b http://onsemi.com 26 package dimensions so ? 16 d suffix case 751b ? 05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a s ituation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP1562A/d the products described herein (ncp1562), may be covered by one or more of the following u.s. patents: 6,771,138. there may be o ther patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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